Vertical NAND string configurations have been used to increase the density of non-volatile memories. One such vertical NAND string structure is discussed in, “Bit Cost Scalable Technology With Punch and Plug Process For Ultra High Density Flash Memory,” by H. Tanaka et al. in Symp. On VLSI Tech. Dig., pp 14˜15(2007). Other approaches are discussed in, for example, Optimal Integration and Characteristics of Vertical Array Devices for Ultra High Density, Bit-Cost Scalable Flash Memory by Y. Fukuzumi et al. in IEDM Tech. Dig., pp-449-452 (2007); U.S. Patent Publication No. U.S.2007/0252201 A1 to Kito et al.; U.S. Pat. No. 6,85,8906; U.S. Pat. No. 7,253,467;U.S. Pat. No. 7,315,474 and U.S. Patent Publication No. 2006/0180851, the disclosures of which are incorporated herein in their entireties.